1. Field
This invention relates, in general, to a memory device, and more particularly a memory device adapted to be connected in a daisy chain and having a data input port and output port that can be selectively enabled, and a memory module and memory system including the same.
2. Description
In general, a memory system includes a memory controller and a plurality of memory module connected to the memory controller. As memory systems having a higher density are demanded, an increasing number of memory modules are employed. Although a memory system with higher density can be obtained by using more memory modules, the capacitive loading of each of the signal lines between the memory controller and memory modules increases. This, in turn, limits the operating speed of the memory system. For this reason, the number of memory devices connected to one data signal line is limited, for example, to eight devices in a memory system employing synchronous dynamic random access memory (SDRAM) to four devices in a memory system employing double data rate (DDR) SDRAM, and to two devices in a memory system employing DDR2/3 SDRAM.
To solve the foregoing problem, a memory system employing a point-to-point (PTP) connection between a memory controller and a memory module has been adopted in memory system architectures. This arrangement is also sometimes referred to as a “daisy chain.” Also, in this PTP arrangement, to increase the density of memory system the memory devices on one memory module employ a stacking package technology including lower memory device 132-1 and upper memory device 134-1 and each memory device is connected by the PTP arrangement.
FIG. 1A is a block diagram of an exemplary memory system 100 having a daisy chain structure. Memory system 100 includes a memory controller 110 and a memory module 120. Memory module 120 includes a plurality of memory groups 130-1˜130-n. In turn, each memory group 130-i includes a primary memory device 132-i and a secondary memory device 134-I which are connected together in a daisy chain or PTP arrangement.
Memory controller 110 includes first output ports (Tx1˜Txn) to output commands, addresses, and write data (C/A/WD) to memory module 120, and first input ports (Rx1˜Rxn) to input read data from memory module 120.
In the memory system 100: C/A/WD indicates merged signal lines for command and addresses and write data for write operations; RD indicates read data lines for read operations; Rx_p indicates an input port of primary memory device 132-i; Rx_s indicates an input port of secondary memory device 134-i; Tx_p indicates an output port of primary memory device 132-I for sending command and addresses and write data; Tx_rdp indicates an output port of primary memory device 132-i for outputting read data; Rx_rdp indicates an input port of primary memory device 132-i; Rx_rds indicates an input port of secondary memory device 134-i for receiving read data; and Tx_rds indicates an output port of secondary memory device 134-i for outputting read data. The input ports Rx_rdp of primary memory devices 132-1˜N are all disabled based upon the memory devices' connection as primary memory devices, rather than secondary memory devices, in the configuration of memory system 100.
Operationally, a read operation of memory system 100 will be explained with reference to FIG. 1A. Consider a case where data is being read out of a primary memory device 132-i to memory controller 110. In that case, read data of the memory device 132-i is transferred to memory controller 110 through the Tx_rdp port of primary memory device 132-i, the Rx_rds port of secondary memory device 134-i, and the Tx_rds port of secondary memory device 134-i, sequentially in that order.
Now, for a read data operation, the Rx_rds port and Tx_rds port of secondary memory device 134-i are always enabled or activated. That is, because secondary memory device 134-i doesn't know when a read operation for primary memory device 132-i occurs and when it will receive the read data from primary memory device 132-i and repeat the read data to memory controller 110, the circuits comprising the Rx_rds port and Tx_rds port of secondary memory device 134-i should always be in an operating condition.
Accordingly, power consumption in memory system 100 is larger than necessary and therefore wasted
FIG. 1B is a block diagram of another exemplary memory system 150 having a daisy chain structure.
Memory system 150 is configured the same as memory system 100 of FIG. 1A, except for the following differences.
While the signal line for commands, addresses, and write data (C/A/WD) is merged in memory system, 100 of FIG. 1A, the signal lines for commands and addresses (C/A) and the signal lines for write data (WD) are separated from each other in memory system 150 of FIG. 1B.
Therefore, in memory system 150 of FIG. 1B, the input ports Rx_rdp of the primary memory devices 132-1˜N are all enabled to receive write data from memory controller 110. Also in a write operation for writing data to secondary memory device 134-i, primary memory device 132-i repeats the write data from memory controller 110 to secondary memory device 134-i through the output port Tx_rdp of primary memory device 132-i. 
That is, the input port Rx_rdp and the output port Tx_rdp of the primary memory device 132-i are always enabled or activated to repeat write data to secondary memory device 134-i because primary memory device 132-i doesn't know when it will have to repeat the write data and output the write data to secondary memory device 134-i. 
Accordingly, power consumption in memory system 150 is larger than necessary and therefore wasted.
Accordingly, it would be advantageous to provide a memory device capable of selectively enabling/disabling an input port and/or an output port depending upon whether the port is needed for a current operation being performed in a memory system in which the memory device operates. It would also be advantageous to provide a memory module including a plurality of such memory devices. It would further be advantageous to provide a memory system including a plurality such a memory module including such a plurality of memory devices.
In one aspect of the invention, a memory device is adapted to be connected in a daisy chain with a memory controller and one or more other memory devices. The memory device comprises: a plurality of memory cells; a data input port adapted to receive read data; a data output port adapted to output the read data; a command/address input port adapted to receive a command and address packet; a decoder adapted to receive and decode the command and address packet and to output one or more detection signals, wherein when the command and address packet includes a read command, the one or more detection signals indicate whether the read command is intended for memory cells of the memory device, or for another memory device in the daisy chain; and a port controller adapted to selectively enable and disable at least one of the data input port and the data output port in response to at least one of the one or more detection signals from the decoder.
In another aspect of the invention, a memory module comprises a plurality of memory devices connected in a daisy chain. Each memory device comprises: a plurality of memory cells; a data input port adapted to receive read data; a data output port adapted to output the read data; a command/address input port adapted to receive a command and address packet; a decoder adapted to receive and decode the command and address packet and to output one or more detection signals, wherein when the command and address packet includes a read command the one or more detection signals indicate whether the read command is intended for memory cells of the memory device, or for one of the other memory device(s) in the daisy chain; and a port controller adapted to selectively enable and disable at least one of the data input port and the data output port in response to at least one of the one or more detection signals from the decoder.
In a further aspect of the invention, a memory system includes: a memory controller; and at least one memory module. Each memory module includes a plurality of memory devices connected in a daisy chain with the memory controller. Each memory device comprises: a plurality of memory cells; a data input port adapted to receive read data; a data output port adapted to output read data; a command/address input port adapted to receive a command and address packet; a decoder adapted to receive and decode the command and address packet and to output one or more detection signals, wherein when the command and address packet includes a read data command the one or more detection signals indicate whether the read data command is intended for memory cells of the memory device, or for one of the other memory device(s) in the daisy chain; and a port controller adapted to selectively enable and disable at least one of the data input port and the data output port in response to at least one detection signal from the decoder.
In yet another aspect of the invention, a memory device is adapted to be connected in a daisy chain with a memory controller and one or more other memory devices. The memory device includes at least one data input port and at least one data output port for communicating data along the daisy-chain between the memory devices and the memory controller. The memory device is adapted to selectively enable/disable at least one of the data input or data output ports in response to whether a command received from the memory controller is intended for the memory device, or for one of the other memory devices.
In still another aspect of the invention, a memory system includes: a memory controller; and at least one memory module. Each memory module includes a plurality of memory devices connected in a daisy chain with the memory controller. Each memory device includes at least one data input port and at least one data output port for communicating data along the daisy-chain between the memory devices and the memory controller, the memory device being adapted to selectively enable/disable at least one of the data input or data output ports in response to whether a command received from the memory controller is intended for the memory device, or for one of the other memory devices.
In a still further aspect of the invention, a memory device is adapted to be connected in a daisy chain with a memory controller and one or more other memory devices. The memory device comprises: a plurality of memory cells; a data input port adapted to receive read data; a data output port adapted to output read data; a command/address input port adapted to receive a command and address packet; a decoder adapted to receive and decode the command and address packet and to output a self read detection signal and a repeat read detection signal, wherein when the command and address packet includes a read command intended for memory cells of the memory device, then the self read detection signal is activated and the repeat read detection signal is inactivated, and when the command and address packet includes a read command intended for another memory device in the daisy chain which is connected to pass the read data to the memory controller through the memory device, then the self read detection signal is inactivated and the repeat read detection signal is activated; and a port controller adapted to selectively enable and disable at least one of the data input port and the data output port in response to at least one of the self read detection signal and the repeat read detection signal.
In an even further aspect of the invention, a memory device is adapted to be connected in a daisy chain with a memory controller and one or more other memory devices. The memory device comprises: a plurality of memory cells; a data input port adapted to receive write data; a data output port adapted to output the write data; a command/address input port adapted to receive a command and address packet; a decoder adapted to receive and decode the command and address packet and to output one or more detection signals, wherein when the command and address packet includes a write command the one or more detection signals indicate whether the write command is intended for memory cells of the memory device, or for one of the other memory device(s) in the daisy chain; and a port controller adapted to selectively enable and disable at least one of the data input port and the data output port in response to at least one detection signal from the decoder.